MIPS MaltaMIPS architecture processor board for MIPS processors (MIPS32 and MIPS64)
||v. 4.x custom BSP |
||MIPS32 RISC, MIPS64 20Kc
||networks, Internet appliances
|Please consult the board-support guide or contact us for specific platform features supported.
The MIPS® Malta™ provides a platform for software development with
MIPS32® and MIPS64® processors. Malta is designed around a standard PC chipset, giving all the
advantages of easy-to-obtain software drivers.
Malta is supplied with the YAMON ROM monitor in the on-board flash memory, which, if
required, can be reprogrammed from a PC or workstation via the IEEE1284 port. The feature set extends
from low-level debugging aids, such as DIP switches, LED displays and logic analyzer connectors, to sophisticated
EJTAG debugger connectivity, audio support, IDE and flash disks and Ethernet. Four PCI slots on the board
give the user a high degree of flexibility enabling the user to extend the functionality of the system.
The development kit features:
- ATX form factor
- Daughter card hosting either an FPGA implementation of a synthesizable core or a lead vehicle
- 100 Mbps Ethernet
- 4 PCI slots
- Audio modem riser connector
- Serial, parallel, USB, keyboard, mouse ports
- IDE and compact flash slots
- 4 Mbytes boot flash
- 64 Mbytes SDRAM
- YAMON™ ROM monitor included
- Sample Linux port included on CD
- EJTAG v2.5 debugger connector
A Malta system is composed of two parts: The Malta motherboard holds the CPU-independent
parts of the circuitry, and the daughter card (CoreLV™, CoreFPGA™ or CoreFPGA2™) hosts
the implementation of the synthesizable core, system controller and fast SDRAM memory. The complete development
kit can be used as a stand-alone or in a suitable ATX chassis. The CoreFPGA and CoreFPGA2 versions are
available for most MIPS cores. CoreFPGA daughtercards use a Galileo system controller; CoreFPGA2 daughter
cards use the SOC-it™ system controller. The FPGA versions have the advantage of being able to accept
new bitstreams for other MIPS cores at some future time (within the constraints of the capacity of the installed FPGA).
Visit MIPS for more information and documentation on the MIPS Malta.