Freescale MPC8548EPowerQUICC III Power Architecture PowerPC networking and telecom processor

Freescale MPC8548E

	v. 4.2
Architecture:	PowerPC / Power Architecture
Processor group:	Freescale MPC85xx PowerQUICC III
Markets:	networks, telecommunications
Please consult the board-support guide or contact us for specific platform features supported.

Key features include 512 KB L2 cache, integrated security engine, 64-bit DDR1/2 scaling to 667 MHz data rate, dual 32-bit PCI or 64-bit PCI-X, 4-bit serial RapidIO fabric technology and 4-bit PCI Express (or single 8-bit PCI Express 1.0a), local bus I/O interfaces, and four GigE interfaces. The combination of these features makes this device an optimal communications processing solution for Ethernet-only or RapidIO interworking applications, such as enterprise networking, telecom transmission and switching and 3G wireless basestations.

The security engine includes Kasumi algorithm acceleration, making the MPC8548E an ideal choice for enhancing security protocol processing in 2.5G and 3G wireless network infrastructure. This device's integrated security also includes XOR acceleration, which enhances system performance by offloading the compute-intensive parity check in small-medium business enterprise (SME) and redundant array of inexpensive disks (RAID) storage applications.

Freescale designed the MPC8548/E processor to offer a wide range of high-speed connectivity options, including GigE, serial RapidIO technology and PCI Express. Support for these high-speed interfaces enables scalable connectivity to network processors and/or ASICs in the data plane while the MPC8548/E handles complex, computationally demanding control plane processing tasks. The MPC8548/E also features a next-generation double data rate (DDR2) memory controller and 3G wireless encryption.

Freescale MPC8548E

• Embedded e500 core, scaling up to 1.5 GHz
  • Dual Dispatch super-scaler, 7-stage pipeline design with out-of-order issue and execution
  • 3065 MIPS at 1333 MHz (estimated Dhrystone 2.1)
• Integrated L1/L2 cache
  • L1 cache/32 KB data and 32 KB instruction cache with line-locking support
  • L2 cache/512 KB (8-way set associative); 512 KB/256 KB/128 KB/64 KB can be used as SRAM
  • L1 and L2 hardware coherency
  • L2 configurable as SRAM, cache or stash cache
• Integrated DDR memory controller with full ECC support, supporting:
  • 200 MHz clock rate (400 MHz data rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
  • 333 MHz clock rate (up to 667 MHz data rate) DDR2 SDRAM
• Double-precision embedded scalar and vector floating-point APUs
• Memory management unit (MMU)
• Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms.
• Multiple PCI interface support
  • 64-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)
  • 64-bit PCI-X bus controller (up to 133 MHz, 3.3V I/O), or
  • Flexibility to configure two 32-bit PCI controllers
• Four on-chip triple-speed Ethernet controllers (GMACs) supporting 10- and 100-Mbps, and 1-Gbps Ethernet/802.3 networks with MII, RMII, GMII, RGMII, RTBI and TBI physical interfaces.
  • TCP/IP checksum acceleration
  • Advanced QoS features
• General-purpose I/O
• Serial RapidIO and PCI Express high-speed interconnect interfaces, supporting
  • Single x8 PCI Express, or
  • Single x4 PCI Express and single 4x Serial RapidIO
• On-chip network (OCeaN) switch fabric
• Integrated four-channel DMA controller
• Dual I²C interfaces and Dual Universal Asynchronous Receiver/Transmitter (DUART) support
• Programmable interrupt controller (PIC)
• General-purpose parallel I/O (GPIO)
• IEEE 1149.1 JTAG test access port
• 1.1V core voltage with 3.3V and 2.5V I/O
• 783-pin FC-BGA package

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