Apple PowerPC G5
 |
v. 4.0 |
 |
v. supported |
 |
v. 5.0 |
| Architecture: |
PowerPC |
| Processor group: |
IBM 970 |
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| Please consult the board-support guide or contact us for specific platform features supported. |
The Apple PowerPC® G5 offers 64-bit processing at speeds
up to 2GHz and can address 8GB main memory. The PowerPC G5 also features an industry-leading 1GHz front-side
bus.
The design of the PowerPC G5 was derived from IBM's 64-bit POWER4 processor, whose highly
parallel processing, two double-precision floating-point units and advanced branch prediction logic drive
IBM's successful eBusiness servers. Apple collaborated with IBM to leverage this industry-leading design
for the G5, combining an optimized Velocity Engine with a new superscalar, superpipelined execution core
that supports more than 200 simultaneous in-flight instructions. This PowerPC architecture has been designed
to scale from 32- to 64-bit.
Features
- L2 Cache: 512K of L2 cache provide the execution core with ultrafast 64-Mbps access
to data and instructions
- L1 Cache: Instructions are prefetched from the L2 cache into a large, direct-mapped
64K L1 cache at 64GBps. In addition, 32K of L1 data cache can prefetch up to eight active data streams
simultaneously.
- Fetch and Decode: As they are accessed from the L1 cache, up to eight instructions
per clock cycle are fetched, decoded and divided into smaller, easier-to-schedule operations.
- Dispatch: Before instructions are dispatched into the functional units, they are
arranged into groups of up to five. Within the core alone, the PowerPC G5 can track up to 20 groups at
a time, or 100 individual instructions.
- Queue: Once an instruction group is dispatched into the execution core, it is broken
into individual instructions, which proceed to the appropriate functional unit, each of which has its
own dedicated queue.
- Optimized Velocity Engine: The PowerPC G5 uses an optimized dual-pipelined Velocity
Engine with two independent queues and dedicated 128-bit registers and data paths for efficient instruction
and data flow.
- Two Double-Precision Floating-Point Units: Two double-precision floating-point units
provide the precision required for highly complex scientific computations and in many of the filters used
to manipulate or render 3D graphics and video content.
- Two Integer Units: The PowerPC G5 has two integer units capable of a broad range
of simple and complex instructions involving both 32-bit or 64-bit calculations, and which take full advantage
of the processor's 64-bit registers and data paths to complete 64-bit integer calculations in a single
pass.
- Load/Store: At the same time as instructions are queued, the load/store units load
the associated data from L1 cache into the data registers behind the units that will be processing the
data, and store it back to L1 cache, L2 cache or main memory after manipulation. With two load/store units,
the PowerPC G5 is able to keep these registers filled with data for maximum processing efficiency.
- Condition Register: This special 32-bit register summarizes the states of the floating-point
and integer units. The condition register also indicates the results of comparison operations and provides
a means for testing them as branch conditions.
- Three Component Branch Prediction Logic: The PowerPC G5 uses branch prediction and
speculative operation to increase efficiency. Like finishing someone else's sentences, branch prediction
anticipates which instruction should go next, and speculative operation causes that instruction to be
executed before it's required. The G5 can predict branch processes with an accuracy of up to 95%.
- Complete: When operations on the data are complete, the PowerPC G5 recombines the
instructions into the original groups of five and the load/store units store the data in cache or main
memory for further processing.
Visit apple.com
for more information on Apple's G5 processor.