AMCC 440GX

	v. 4.0
	v. 5.1, 5.0
Architecture:	PowerPC
Processor group:	AMCC 440 (formerly IBM 440)
Markets:	storage, networks
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The AMCC PowerPC® 440GX processor offers the versatility and bandwidth required for today's demanding networking and storage applications. The 440GX expands the 440 family by delivering both higher performance and increased function. For users requiring higher performance, the 440GX delivers up to 667MHz while maintaining pin and software compatibility. In addition, new functions such as Gigabit Ethernet, integrated L2 cache, I2O Messaging Unit, and TCP/IP acceleration hardware deliver significant value. A PCI-X interface that supports frequencies of up to 133 MHz and an on-chip double data rate (DDR) SDRAM controller, supporting up to DDR333, further enhance processor capabilities.

With embedded state-of-the-art peripheral cores, the 440GX processor is ideal for networking control plane applications, RAID controllers, iSCSI processing, and storage area networking (SAN) equipment. I/O processing applications can benefit from the integrated messaging unit, designed to the I2O specification. This messaging unit improves system performance by enabling the 440GX processor to communicate using I2O messages with a host system on the PCI bus. This allows the processor to work as an intelligent I/O adapter controller. The 256KB on-chip SRAM can be configured either as a performance enhancing L2 cache, or as memory-mapped SRAM for low-latency access. Used as an L2, the 256KB SRAM is a 4-way set-associative, unified data instruction cache, which can benefit many applications. As memory-mapped SRAM, it has lower memory-access latency than the SDRAM, offering quick access to crucial code or data. Software-controlled and with parity support, this memory is ideal for storing data packets, critical code segments, Ethernet or DMA descriptors, or other application-specific data. When configured as a memory-mapped region, this SRAM is accessible from any PLB master, which can further improve application performance.

The 440GX integrates four Ethernet media access controllers (MACs), including two 10/100 Mb interfaces and two 10/100/1Gb interfaces with support for jumbo packets and TCP/IP acceleration hardware (TAH). These MACs offer both flexibility and high performance. For example, they can be configured to provide four SMII interfaces for maximum connectivity, or dual gigabit interfaces for high-speed communications, plus one or two Fast Ethernet interfaces for other application requirements.

Many networking and storage applications can benefit from the PowerPC 440GX software-enabled TCP/IP hardware-assist state machine that accelerates datapacket processing. This TCP/IP engine relieves the CPU of the checksum and transmit segmentation workload, making it available to handle other application demands.

The PowerPC 440GX processor is a 32-bit implementation of the Book E Enhanced PowerPC Architecture that ensures code compatibility across all PowerPC processors. The 440GX design implements the CoreConnect™ bus architecture with a 166MHz Processor Local Bus (PLB) that includes 128-bit read and write data buses and a separate 36-bit address bus. The processor also has an 83MHz on-chip peripheral bus (OPB) that supports the 36-bit address bus, as well as a 32-bit data bus that can dynamically resize to 16 or 8 bits, depending on the transaction. Conformance to these architectures facilitates and can help to reduce the cost of application development and migration.

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